1. Field of the Invention
The present invention relates generally to electronic circuits. More specifically, the present invention relates to a current steering folding circuit which may be used in an analog-to-digital converter (ADC).
2. Description of Related Art
The rapid expansion of digital signal processing across large and diverse sets of applications has made the ADC an important functional building block in most analog/digital very large-scale integration (VLSI) systems. Applications such as wireless communications, flat-panel displays and hand-held multimedia devices require highspeed ADCs with low power dissipation.
Several types of ADCs are known in the art. For example, a “flash” ADC utilizes a set of comparators operating in parallel, each comparing the analog input signal to a different reference voltage. The flash ADC is one of the fastest presently-known ADC architectures. However, the exponential growth of power, area and input capacitance of flash ADCs as a function of resolution makes them impractical for resolution above 8 bits.
Another type of ADC utilizes a “folding” circuit. In such an ADC, an analog input signal is applied to a coarse quantizer and a folding circuit. The coarse quantizer determines the most significant bits of the digital output signal. The folding circuit linearly “folds” the analog input signal to provide a folded output signal. The range of the folded output signal is smaller than the range of the analog input signal. The folded output signal is then provided to a fine quantizer. The fine quantizer determines the least significant bits of the digital output signal.
Typically, the folded output signal is proportional to the difference between two signals that have a plurality of zero crossing points (i.e., points where the signals are equal) when measured against an increasing input signal. The number of periodic piece-wise linear segments, or folds, in the input-output transfer characteristics of the folding circuit corresponds to the number of zero crossing points and is referred to as the folding factor of the circuit.
In a conventional folding circuit, N+1 current sources are required for a folding circuit with a folding factor of N. There are several drawbacks associated with this approach. First, mismatches in the current sources may cause output offset errors at the zero crossing points. Second, the use of N+1 current sources causes excessive capacitive loading at the output of the folding circuit, which limits the sampling frequency of the fine quantizer. Finally, the use of N+1 current sources requires a great deal of power.
Accordingly, it would be an advancement in the art if means were provided to overcome one or more of the above problems.